1. Field of the Invention
This invention relates to a nonvolatile semiconductor memory device and a method for manufacturing the same.
2. Background Art
Conventionally, nonvolatile semiconductor memory devices such as flash memories have been fabricated by two-dimensionally integrating elements on the surface of a silicon substrate. Increasing the memory capacity of such a flash memory needs to rely on downscaling by decreasing the dimensions of each element. However, such downscaling has recently been difficult in terms of cost and technology.
To solve this problem, numerous methods for three-dimensionally integrating elements are proposed. Among them, a simultaneously processed three-dimensional multilayer memory having high productivity is promising (see JP-A 2007-266143 (Kokai)). In this technique, electrode films and insulating films are alternately stacked on a silicon substrate to form a multilayer body, and then through holes are simultaneously formed in this multilayer body. A charge storage layer is formed on the side surface of the through hole, and silicon is buried inside the through hole to form a silicon pillar. Thus, a memory cell is formed at each intersection between the electrode film and the silicon pillar. Furthermore, the end portion of the multilayer body is processed into a staircase shape, an interlayer insulating film is provided around the multilayer body so as to overlap the staircase-shaped end portion, and contacts are buried in the interlayer insulating film so as to be connected to the end portions of the electrode films. A plurality of metal interconnects are provided above the interlayer insulating film and connected to the end portions of the electrode films through the contacts. Thus, the potential of each electrode film can be independently controlled through the metal interconnect and the contact.
In this simultaneously processed three-dimensional multilayer memory, information can be recorded by controlling the potential of each electrode film and each silicon pillar to transfer charge between the silicon pillar and the charge storage layer. In this technique, a plurality of electrode films are stacked on the silicon substrate to reduce the chip area per bit, and it allows cost reduction. Furthermore, because the multilayer body can be simultaneously processed to form a three-dimensional multilayer memory, increase in the number of stacked films does not result in increasing the number of lithography steps, and cost increase can be suppressed.
In this simultaneously processed three-dimensional multilayer memory, three layers of a tunnel insulating film, a charge storage layer, and a block insulating film are provided inside the through hole. This restricts reduction of the diameter of the through hole, and there is room for improvement for higher density packaging.